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To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices.
Renesas Technology Corp. Customer Support Dept. April 1, 2003
2002.04.18
Ver. 6.0
MITSUBISHI LSIs
M5M5W816WG - 55HI, 70HI, 85HI
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5W816 is a f amily of low v oltage 8-Mbit static RAMs organized as 524288-words by 16-bit, f abricated by Mitsubishi's high-perf ormance 0.18m CMOS technology . The M5M5W816 is suitable f or memory applications where a simple interf acing , battery operating and battery backup are the important design objectiv es. M5M5W816WG is packaged in a CSP (chip scale package), with the outline of 7.5mm x 8.5mm, ball matrix of 6 x 8 (48ball) and ball pitch of 0.75mm. It giv es the best solution f or a compaction of m ounting area as well as f lexibility of wiring pattern of printed circuit boards.
FEATURES
Single 2.7~3.6V power supply Small stand-by current: 0.1A (2V, ty p.) No clocks, No ref resh Data retention supply v oltage =2.0V All inputs and outputs are TTL compatible. Easy memory expansion by S1#, S2, BC1# and BC2# Common Data I/O Three-state outputs: OR-tie capability OE prev ents data contention in the I/O bus Process technology : 0.18m CMOS Package: 48ball 7.5mm x 8.5mm CSP
Version, Operating temperature Part name M5M5W816WG -55HI
Power Supply
Access time
max.
55ns
Stand-by c urrent (A) * Ty pical(3.0V) Ratings (max.@ Vcc=3.6V) 25C 0.5
Activ e current Icc1 40C 25C 40C 70C 85C *(3.0V, ty p.) 1.0 5.0 8.0 20 40
30mA (10MHz) 5mA (1MHz)
I-version
-40 ~ +85C
M5M5W816WG -70HI M5M5W816WG -85HI
2.7 ~ 3.6V
70ns 85ns
* Typical parameter indicates the value for the center of distribution, and is not 100% tested.
PIN CONFIGURATION
(TOP VIEW)
1 A B C D E F G H
BC1#
2
OE#
3
A0
4
A1
5
A2
6
S2
DQ16
BC2#
A3
A4
S1#
DQ1
Pin
DQ14 DQ15 A5 A6 DQ2 DQ3
Function Address input Chip select input 1 Chip select input 2 Write control input Output enable input Lower By te (DQ1 ~ 8) Upper By te (DQ9 ~ 16) Power supply Ground supply
A0 ~ A18 S1# S2 W# OE# BC1# BC2# Vcc GND
DQ1 ~ DQ16 Data input / output
GND DQ13 A17 A7 DQ4 VCC
VCC
DQ12
NC or GND
A16
DQ5
GND
DQ11
DQ10
A14
A15
DQ7
DQ6
DQ9
N.C.
A12
A13
W#
DQ8
A18
A8
A9
A10
A11
N.C.
Outline : 48F7Q NC : No Connection *Don't connect E3 ball to voltage level more than 0V.
1
2002.04.18
Ver. 6.0
MITSUBISHI LSIs
M5M5W816WG - 55HI, 70HI, 85HI
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
FUNCTION
The M5M5W816WG is organized as 524288-words by 16-bit. These dev ices operate on a single +2.7~3.6V power supply , and are directly TTL compatible to both input and output. Its f ully static circuit needs no clocks and no ref resh, and makes it usef ul. The operation mode are determined by a combination of the dev ice control inputs BC1# , BC2# , S1#, S2 , W# and OE#. Each mode is summarized in the f unction table. A write operation is executed whenev er the low lev el W# ov erlaps with the low lev el BC1# and/or BC2# and the low lev el S1# and the high lev el S2. The address(A0~A18) must be set up bef ore the write cy c le and must be stable during the entire cycle. A read operation is executed by s etting W# at a high lev el and OE# at a low lev el while BC1# and/or BC2# and S1# and S2 are in an activ e state(S1#=L,S2=H). When setting BC1# at the high lev el and other pins are in an activ e stage , upper-by t e are in a selectable mode in which both reading and writing are enabled, and lower-by t e are in a non-selectable mode. And when setting BC2# at a high lev el and other pins are in an activ e stage, lower-by t e are in a selectable mode and upper-by te are in a nonselectable mode.
When setting BC1# and BC2# at a high lev el or S1# at a high lev el or S2 at a low lev el, the chips are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by BC1#, BC2# and S1#, S2. The power supply c urrent is reduced as low as 0.1A(25C, ty pical), and the memory data can be held at +2.0V power supply , enabling battery back-up operation during power f ailure or power-down operation in the non-selected mode.
FUNCTION TABLE
S1# S2 BC1# BC2# W# OE#
Mode
Non selection Non selection Non selection Non selection
DQ1~8
DQ9~16
H L H X L L L L L L L L L
L L H X H H H H H H H H H
X X X H L L L H H H L L L
X X X H H H H L L L L L L
X X X X L H H L H H L H H
X X X X X L H X L H X L H
Write Read Write Read Write Read
High-Z High-Z High-Z High-Z Din Dout High-Z High-Z High-Z High-Z Din Dout High-Z
High-Z High-Z High-Z High-Z High-Z High-Z High-Z Din Dout High-Z Din Dout High-Z
Icc Standby Standby Standby Standby Activ e Activ e Activ e Activ e Activ e Activ e Activ e Activ e Activ e
BLOCK DIAGRAM
A0 A1
(note1) "H" and "L" in this table mean VIH and VIL, respectiv ely . (note2) "X" in this table should be "H" or "L".
DQ 1
MEMORY ARRAY 524288 WORDS x 16 BITS A17 A18
S1# S2 CLOCK GENERATOR -
DQ 8
DQ 9
DQ 16
BC1#
BC2#
Vcc
W#
GND
OE#
2
2002.04.18
Ver. 6.0
MITSUBISHI LSIs
M5M5W816WG - 55HI, 70HI, 85HI
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Supply v oltage Input v oltage Output v oltage Power dissipation Operating temperature Storage temperature Conditions With respect to GND With respect to GND With respect to GND Ta= 25C Ratings Units
Vcc VI VO Pd Ta T stg
-0.3* ~ +4.6 -0.3* ~ Vcc + 0.3 (max. 4.6V) 0 ~ Vcc 700 - 40 ~ +85 - 65 ~ +150
V mW
C C
* -3.0V in case of AC (Pulse width < 30ns)
DC ELECTRICAL CHARACTERISTICS
Symbol
( Vcc=2.7 ~ 3.6V, unless otherwise noted) Limits Min Ty p Max Vcc+0.2V Units
Parameter High-lev el input v oltage Low-lev el input v oltage High-lev el output v oltage IOH= -0.5mA Low-lev el output v oltage IOL=2mA Input leakage current Output leakage current ( AC,MOS lev el )
Conditions
VIH VIL VOH VOL II IO
2.2 -0.2 * 2.4
0.6 0.4 1 1 50 15 50 15 5 8 20 40 2
V
VI =0 ~ Vcc
BC1# and BC2# =VIH or S1# =VIH or S2=VIL or OE# =VIH, VI/O=0 ~ Vcc BC1# and BC2# < 0.2V, S1# < 0.2V, S2 > Vcc-0.2V other inputs < 0.2V or > Vcc-0.2V Output - open (duty 100%)
A
Icc1 Activ e supply c urrent
f = 10MHz f = 1MHz f = 10MHz f = 1MHz ~ +25C ~ +40C ~ +70C ~ +85C
Activ e supply c urrent Icc2 ( AC,TTL lev el )
BC1# and BC2#=V IL , S1#=V IL ,S2=V IH other pins =V IH or VIL Output - open (duty 100%) (1) S1# > Vcc - 0.2V,
S2 > Vcc - 0.2V, other inputs = 0 ~ Vcc
-
30 5 30 5 0.5 1.0 -
mA
Icc3 Stand by s upply current
( AC,MOS lev el )
(2) S2 < 0.2V,
other inputs = 0 ~ Vcc
A
(3) BC1# and BC2# > Vcc - 0.2V
S1# < 0.2V, S2 > Vcc - 0.2V other inputs = 0 ~ Vcc
Icc4
Stand by s upply current ( AC,TTL lev el )
BC1# and BC2# =VIH or S1# =VIH or S2 =VIL Other inputs= 0 ~ Vcc
mA
Note 1: Direction for current flowing into IC is indicated as positive (no mark).
* -1.0V in case of AC (Pulse width < 30ns)
Note 2: Typical parameter indicates the value for the center of distribution at 3.0V, and is not 100% tested.
CAPACITANCE
Symbol Parameter Input capacitance Output capacitance Conditions
(Vcc=2.7 ~ 3.6V, unless otherwise noted) Limits Ty p Units
Min VI=GND, VI=25mVrms, f =1MHz VO=GND,VO=25mVrms, f =1MHz
Max
CI CO
10 10
pF
3
2002.04.18
Ver. 6.0
MITSUBISHI LSIs
M5M5W816WG - 55HI, 70HI, 85HI
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (1) TEST CONDITIONS
Supply v oltage
(Vcc=2.7 ~ 3.6V, unless otherwise noted)
2.7~3.6V Input pulse VIH=2.4V, VIL=0.4V Input rise time and f all time 5ns
Ref erence lev el Output loads
1TTL DQ CL
Including scope and jig capacitance
VOH=VOL=1.5V
Transition is measured 200mV from steady state voltage.(for ten,tdis)
Fig.1,CL=30pF CL=5pF (for ten,tdis)
Fig.1 Output load
(2) READ CYCLE
Limits Symbol tCR Parameter Read cy cle time Address access time Chip select 1 access time Chip select 2 access time By te control 1 access time By te control 2 access time Output enable access time Output disable time af t er S1# high Output disable time af t er S2 low Output disable time af t er BC1# high Output disable time af t er BC2# high Output disable time af t er OE# high Output enable time af ter S1# low Output enable time af ter S2 high Output enable time af ter BC1# low Output enable time af ter BC2# low Output enable time af ter OE# low Data v alid time after address Min 55 55HI Max 55 55 55 55 55 30 20 20 20 20 20 10 10 5 5 5 10 10 10 5 5 5 10 Min 70 70HI Max 70 70 70 70 70 35 25 25 25 25 25 10 10 5 5 5 10 Min 85 85HI Max 85 85 85 85 85 45 30 30 30 30 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units
ta(A) ta(S1) ta(S2) ta(BC1) ta(BC2) ta(OE) tdis (S1) tdis (S2) tdis (BC1) tdis (BC2) tdis (OE) ten(S1) ten(S2) ten(BC1) ten(BC2) ten(OE) tV(A)
(3) WRITE CYCLE
Limits Symbol Parameter Write cy cle time Write pulse width Address setup time Address setup time with respect to W# By te control 1 setup time By te control 2 setup time Chip select 1 setup time Chip select 2 setup time Data setup time Data hold time Write recov ery time Output disable time f rom W# low Output disable time f rom OE# high Output enable time f rom W# high Output enable time f rom OE# low Min 55 45 0 50 50 50 50 50 30 0 0 55HI Max Min 70 55 0 65 65 65 65 65 35 0 0 70HI Max Min 85 60 0 70 70 70 70 70 45 0 0 85HI Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units
tCW tw(W) tsu(A) tsu(A-WH) tsu(BC1) tsu(BC2) tsu(S1) tsu(S2) tsu(D) th(D) trec(W) tdis (W) tdis (OE) ten(W) ten(OE)
20 20 5 5 5 5
25 25 5 5
30 30
4
2002.04.18
Ver. 6.0
MITSUBISHI LSIs
M5M5W816WG - 55HI, 70HI, 85HI
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS Read cycle
A0~18 ta(A) BC1#,BC2#
(Note3)
tCR
tv (A)
ta(BC1) or ta(BC2) tdis (BC1) or tdis (BC1) ta(S1)
(Note3) (Note3)
S1#
tdis (S1) ta(S2)
(Note3)
S2
(Note3)
tdis (S2) ta (OE)
(Note3)
OE#
(Note3) W# = "H" lev el
ten (OE) ten (BC1) ten (BC2) ten (S1) ten (S2) tCW
tdis (OE)
(Note3)
DQ1~16
VALID DATA
Write cycle ( W# control mode )
A0~18
tsu (BC1) or tsu(BC2) BC1#,BC2#
(Note3) (Note3)
S1#
(Note3)
tsu (S1)
(Note3)
S2
(Note3)
tsu (S2)
(Note3)
OE# tsu (A) W# tdis(OE) DQ1~16
tsu (A-WH) tw (W) tdis (W)
trec (W) ten(OE) ten (W)
DATA IN STABLE
tsu (D)
th (D)
5
2002.04.18
Ver. 6.0
MITSUBISHI LSIs
M5M5W816WG - 55HI, 70HI, 85HI
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
Write cycle (BC# control mode)
A0~18 tsu (A) BC1#,BC2# S1#
(Note3)
tCW
tsu (BC1) or tsu (BC2)
trec (W)
(Note3)
S2
(Note3) (Note5) (Note4) (Note3) (Note3) (Note3)
W#
tsu (D) DQ1~16
DATA IN STABLE
th (D)
Note 3: Hatching indicates the state is "don't care". Note 4: A Write occurs during S1# low, S2 high overlaps BC1# and/or BC2# low and W# low. Note 5: When the falling edge of W# is simultaneously or prior to the falling edge of BC1# and/or BC2# or the falling edge of S1# or rising edge of S2, the outputs are maintained in the high impedance state. Note 6: Don't apply inverted phase signal externally when DQ pin is in output mode.
6
2002.04.18
Ver. 6.0
MITSUBISHI LSIs
M5M5W816WG - 55HI, 70HI, 85HI
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
Write cycle (S1# control mode)
A0~18
tCW
BC1#,BC2#
(Note3)
tsu (A)
tsu (S1)
trec (W)
(Note3)
S1#
S2
(Note3) (Note5) (Note3)
W#
(Note3)
(Note4)
tsu (D)
DATA IN STABLE
th (D)
(Note3)
DQ1~16
Write cycle (S2 control mode)
A0~18
tCW
BC1#,BC2#
(Note3)
tsu (A)
tsu (S2)
trec (W)
(Note3)
S1#
S2
(Note3) (Note5) (Note3)
W#
(Note3)
(Note4)
tsu (D)
DATA IN STABLE
th (D)
(Note3)
DQ1~16
7
2002.04.18
Ver. 6.0
MITSUBISHI LSIs
M5M5W816WG - 55HI, 70HI, 85HI
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS
Symbol Vcc Parameter Test conditions Min Limits Ty p Max Units V
Vcc(PD)
(PD) Power down supply voltage Byte control input BC1# & BC2#
2.0
2.2V < Vcc(PD) 2.0V < Vcc(PD) < 2.2V 2.2V < Vcc(PD) 2.0V < Vcc(PD) < 2.2V
VI (BC)
2.2 2.2
Vcc(PD)
V
VI (S1) VI (S2)
Chip select input S1# Chip select input S2
V
0.2
Vcc=2.0V
(1) S1# > Vcc - 0.2V,
~ +25C ~ +40C ~ +70C ~ +85C
-
0.1 0.2 -
1.5 3 15 30 A
Icc
(PD)
Power down supply c urrent
other inputs = 0 ~ Vcc (2) S2 < 0.2V, other inputs = 0 ~ Vcc (3) BC1# and BC2# > Vcc - 0.2V S1# < 0.2V, S2 > Vcc - 0.2V other inputs = 0 ~ Vcc
(2) TIMING REQUIREMENTS
Symbol Parameter Power down set up time Power down recov ery t ime
Note 7: Typical parameter of Icc(PD) indicates the value for the center of distribution, and is not 100% tested.
Limits Test conditions Min Ty p Max
Units ns ms
tsu (PD) trec (PD)
0 5
(3) TIMING DIAGRAM
BC# control mode On the BC# control mode, the lev el of S1# and S2 must be f ixed at S1#, S2 > Vcc-0.2V or S2 < 0.2V.
Vcc tsu (PD) 2.2V BC1# BC2#
S1# control mode
2.7V
2.7V
trec (PD) 2.2V
BC1# , BC2# > Vcc-0.2V
On the S1# control mode, the lev el of S2 must be f ixed at S2 > Vcc-0.2V or S2 < 0.2V.
Vcc tsu (PD) 2.2V S1#
S2 control mode
2.7V
2.7V
trec (PD) 2.2V
S1# > Vcc-0.2V
Vcc S2 tsu (PD) 0.2V S2 < 0.2V 0.2V 2.7V 2.7V trec (PD)
8
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